Capacitor formed on a recrystallized polysilicon layer and a method of manufacture therefor

ABSTRACT

The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, among other elements, includes a recrystallized polysilicon layer  148  located over a gate electrode layer  143 , a capacitor  170  located on the recrystallized polysilicon layer  148 . The capacitor  170 , in this embodiment, includes a first electrode  173 , an insulator  175  located over the first electrode  173 , and a second electrode  178  located over the insulator  175.

TECHNICAL FIELD OF THE INVENTION

The present invention is directed, in general, to a semiconductor deviceand, more specifically, to a capacitor formed on a recrystallizedpolysilicon layer and a method of manufacture therefor.

BACKGROUND OF THE INVENTION

Modern electronic equipment such as televisions, telephones, radios andcomputers are generally constructed of solid state devices. Solid statedevices are preferred in electronic equipment because they are extremelysmall and relatively inexpensive. Additionally, solid state devices arevery reliable because they have no moving parts, but are based on themovement of charge carriers.

Solid state devices may be transistors, capacitors, resistors and othersemiconductor devices. Typically, such devices are fabricated on asubstrate and interconnected to form memory arrays, logic structures,timers and other integrated circuits. One type of memory array is adynamic random access memory (DRAM) in which memory cells retaininformation only temporarily and are refreshed at periodic intervals.Despite this limitation, DRAMs are widely used because they provide lowcost per bit of memory, high device density and feasibility of use.

In a DRAM, each memory cell typically includes an access transistorcoupled to a storage capacitor. In order to fabricate high densityDRAMs, the storage capacitors must take up less planar area in thememory cells. As storage capacitors are scaled down in dimensions, asufficiently high storage capacity must be maintained. Efforts tomaintain storage capacity have concentrated on buildingthree-dimensional capacitor structures that increase the capacitorsurface area. The increased surface area provides for increased storagecapacity. Three-dimensional capacitor structures typically includetrench capacitors and stacked capacitors. While trench capacitors arestill used, many of the capacitors currently used are of the stackedcapacitor type.

Stacked capacitors typically include first and second conductiveelectrodes separated by an insulative material. Often the first, orlower electrode, comprises a material such as cobalt silicide, theinsulative material comprises a material such as silicon dioxide, andthe second, or upper electrode, comprises a material such as titaniumnitride. This is particularly the case when striving for highperformance capacitors.

While the above-discussed capacitors are used as high performancecapacitors, their use is not without certain drawbacks. One suchdrawback stems from the difficulty in forming substantially planarfirst, or lower electrodes. Specifically, the first, or lowerelectrodes, presently have varying and unpredictable amounts ofroughness. This unfortunately, causes the capacitors to have varying andunpredictable amounts of capacitance, as a result of the increased ordecreased surface area of the first, or lower electrode. It has beenobserved that the varying and unpredictable amounts of roughness areparticularly evident when the first, or lower electrode, is formed overa polysilicon substrate. Unfortunately, these capacitors are oftenformed directly on the polysilicon gate of the underlying transistor,which exaggerates this problem.

Accordingly, what is needed in the art is a capacitor that does notexperience the lower electrode roughness experienced by the prior artcapacitors.

SUMMARY OF THE INVENTION

To address the above-discussed deficiencies of the prior art, thepresent invention provides a semiconductor device, a method ofmanufacture therefor, and an integrated circuit including thesemiconductor device. The semiconductor device, among other elements,includes a recrystallized polysilicon layer located over a gateelectrode layer, and a capacitor located on the recrystallizedpolysilicon layer. The capacitor, in this embodiment, includes a firstelectrode, an insulator located over the first electrode, and a secondelectrode located over the insulator.

In addition to the semiconductor device, the present invention providesa method of manufacturing the semiconductor device. The method formanufacturing the semiconductor device includes forming an amorphoussilicon layer over a substrate, then changing the amorphous siliconlayer to a recrystallized polysilicon layer. The method further includescreating a capacitor on the recrystallized polysilicon layer, whereinthe capacitor includes a first electrode, an insulator located over thefirst electrode, and a second electrode located over the insulator.

The present invention, as mentioned above, further includes anintegrated circuit. The integrated circuit includes 1) transistorslocated over a substrate, wherein at least one of the transistorsincludes a gate electrode stack comprising a recrystallized polysiliconlayer located over a gate electrode layer, 2) a capacitor located on therecrystallized polysilicon layer, wherein the capacitor includes a firstelectrode, an insulator located over the first electrode, and a secondelectrode located over the insulator, and 3) an interlevel dielectriclayer located over the substrate, the interlevel dielectric layer havinginterconnects located therein for contacting at least one of the gateelectrode stack or the capacitor.

The foregoing has outlined preferred and alternative features of thepresent invention so that those skilled in the art may better understandthe detailed description of the invention that follows. Additionalfeatures of the invention will be described hereinafter that form thesubject of the claims of the invention. Those skilled in the art shouldappreciate that they can readily use the disclosed conception andspecific embodiment as a basis for designing or modifying otherstructures for carrying out the same purposes of the present invention.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is best understood from the following detailed descriptionwhen read with the accompanying FIGUREs. It is emphasized that inaccordance with the standard practice in the semiconductor industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion. Reference is now made to the following descriptions taken inconjunction with the accompanying drawings, in which:

FIG. 1A illustrates a cross-sectional view of one embodiment of asemiconductor device constructed according to the principles of thepresent invention;

FIG. 1B illustrates an embodiment of the present invention wherein anadditional layer, or layers, of material interpose the gate electrodelayer and the recrystallized polysilicon layer;

FIG. 2 illustrates a cross-sectional view of a partially completedsemiconductor device;

FIG. 3 illustrates a cross-sectional view of the partially completedsemiconductor device illustrated in FIG. 2 after formation of a gatestructure over the substrate;

FIG. 4 illustrates a cross-sectional view of the partially completedsemiconductor device illustrated in FIG. 3 after formation of lightlydoped extension implants within the substrate;

FIG. 5 illustrates a cross-sectional view of the partially completedsemiconductor device illustrated in FIG. 4 after formation ofconventional gate sidewall spacers and after formation of highly dopedsource/drain implants within the substrate;

FIG. 6 illustrates a cross-sectional view of the partially completedsemiconductor device illustrated in FIG. 5 after subjecting it to astandard source/drain anneal thereby activating source/drain regions;

FIG. 7 illustrates a cross-sectional view of the partially completedsemiconductor device illustrated in FIG. 6 after depositing a firstelectrode layer on the recrystallized polysilicon layer;

FIG. 8 illustrates a cross-sectional view of the partially completedsemiconductor device illustrated in FIG. 7 after subjecting the firstelectrode layer of FIG. 7 to a first rapid thermal anneal (RTA) processand a selective wet etch process;

FIG. 9 illustrates a cross-sectional view of the partially completedsemiconductor device illustrated in FIG. 8 after subjecting the firstelectrode layer of FIG. 8 to a second rapid thermal anneal (RTA)process;

FIG. 10 illustrates sheet resistance (Rs) and surface nonuniformity (NU%) for three different situations of devices;

FIG. 11 illustrates a graph showing the surface roughness measured usingan atomic force microscope (AFM) of samples similar to the threedifferent situations illustrated in FIG. 10;

FIG. 12 illustrates a comparison of the inversion capacitance of apolysilicon gate electrode layer and a recrystallized polysilicon gateelectrode layer; and

FIG. 13 illustrates a cross-sectional view of a conventional integratedcircuit (IC) incorporating devices constructed according to theprinciples of the present invention.

DETAILED DESCRIPTION

Referring initially to FIG. 1A, illustrated is a cross-sectional view ofone embodiment of a semiconductor device 100 constructed according tothe principles of the present invention. In the embodiment illustratedin FIG. 1A, the semiconductor device 100 includes a substrate 110.Located within the substrate 110 in the embodiment of FIG. 1A is a wellregion 120. Additionally, located over the substrate 110 and well region120 is a gate structure 130.

The gate structure 130 illustrated in FIG. 1A includes a gate oxide 135located over the substrate 110, as well as a gate electrode stack 140located over the gate oxide 135. In the particular embodiment shown, thegate electrode stack 140 includes a gate electrode layer 143, such as apolysilicon gate electrode, and a recrystallized polysilicon layer 148located over the gate electrode layer 143. The recrystallizedpolysilicon layer 148 may have a final thickness that ranges from about7 nm to about 35 nm, among others. Flanking both sides of the gateelectrode stack 140 and gate oxide 135 of the gate structure 130depicted in FIG. 1A are gate sidewall spacers 150.

The semiconductor device 100 illustrated in FIG. 1A further includesconventional source/drain regions 160 located within the substrate 110.The source/drain regions 160, as is common, may each include a lightlydoped extension implant 163 as well as a higher doped source/drainimplant 168.

Located on the recrystallized polysilicon layer 148 of the gateelectrode stack 140 is a capacitor 170. The capacitor 170, which oftenis a high performance capacitor, includes a first electrode 173, or inthis instance a lower electrode, located on the recrystallizedpolysilicon layer 148. The capacitor 170 further includes an insulator175 located over the first electrode 173, as well as a second electrode178, or in this instance an upper electrode, located over the insulator175.

Unique to the present invention, the first electrode 173, which maycomprise a silicide or more particularly a cobalt silicide, may have areduced surface roughness. For example, the first electrode 173 may havea surface roughness less than about 2.5 nm, or in an exemplaryembodiment a surface roughness ranging from about 1 nm to about 2 nm. Asthe first electrode 173 is formed on the recrystallized polysiliconlayer 148 rather than a conventional polysilicon layer or anotherdifferent material, these reduced surface roughness values areattainable. The first electrode, among others, may also have a thicknessthat ranges from about 15 nm to about 70 nm.

While the embodiment of FIG. 1A illustrates that the recrystallizedpolysilicon layer 148 is located on the gate electrode layer 143, thoseskilled in the art understand that this must not always be the case. Forinstance, turning to FIG. 1B, illustrated is an embodiment of thepresent invention wherein an additional layer 180, or layers, ofmaterial interpose the gate electrode layer 143 and the recrystallizedpolysilicon layer 148. In this instance the first electrode 173 wouldstill be located on the recrystallized polysilicon layer 148, therebyproviding the desired surface roughness, however, the recrystallizedpolysilicon layer 148 would not be located on the gate electrode layer143, but over the gate electrode layer 143.

Turning now to FIGS. 2-9, illustrated are cross-sectional views ofdetailed manufacturing steps instructing how one might, in anadvantageous embodiment, manufacture a semiconductor device similar tothe semiconductor device 100 depicted in FIG. 1A. FIG. 2 illustrates across-sectional view of a partially completed semiconductor device 200.The partially completed semiconductor device 200 of FIG. 2 includes asubstrate 210. The substrate 210 may, in an exemplary embodiment, be anylayer located in the partially completed semiconductor device 200,including a wafer itself or a layer located above the wafer (e.g.,epitaxial layer). In the embodiment illustrated in FIG. 2, the substrate210 is a P-type semiconductor substrate; however, one skilled in the artunderstands that the substrate 210 could be an N-type substrate withoutdeparting from the scope of the present invention. In such a case, eachof the dopant types described throughout the remainder of this documentwould be reversed. For clarity, no further reference to this oppositescheme will be discussed.

Located within the substrate 210 in the embodiment shown in FIG. 2 areshallow trench isolation regions 220. The shallow trench isolationregions 220 isolate the semiconductor device 200 from other deviceslocated proximate thereto. As those skilled in the art understand thevarious steps used to form these conventional shallow trench isolationregions 220, no further detail will be given.

In the illustrative embodiment of FIG. 2, also formed within thesubstrate 210 is a well region 230. The well region 230, in light of theP-type semiconductor substrate 210, would more than likely contain anN-type dopant. For example, the well region 230 would likely be dopedwith an N-type dopant dose ranging from about 1E13 atoms/cm² to about1E14 atoms/cm² and at a power ranging from about 100 keV to about 500keV. What generally results in the well region 230 having a peak dopantconcentration ranging from about 5E17 atoms/cm³ to about 1E19 atoms/cm³.

Turning now to FIG. 3, illustrated is a cross-sectional view of thepartially completed semiconductor device 200 illustrated in FIG. 2 afterformation of a gate structure 310 over the substrate 210. As isillustrated in FIG. 3, the gate structure 310 includes a gate oxide 320and a gate electrode stack 330. Unique to the present invention, at thispoint in the manufacturing process the gate electrode stack 330comprises a polysilicon gate electrode 333 and an amorphous siliconlayer 338.

To form the gate structure 310 shown in FIG. 3, a thin gate oxide layer,a thicker polysilicon gate electrode layer and a medium thicknessamorphous silicon layer are conventionally deposited on top of oneanother and then patterned, resulting in the gate structure 310 shown inFIG. 3. For example, the polysilicon gate electrode layer could bedeposited using a pressure ranging from about 100 torr to about 300torr, a temperature ranging from about 620° C. to about 700° C., and aSiH₄ gas flow ranging from about 50 sccm to about 150 sccm. Similarly,the amorphous silicon layer could be deposited using a pressure rangingfrom about 100 torr to about 300 torr, a temperature ranging from about450° C. to about 550° C., and a SiH₄ gas flow ranging from about 100sccm to about 300 sccm.

While the thickness of the gate oxide may vary greatly, in anadvantageous embodiment of the present invention the thickness of thepolysilicon gate electrode 333 should range from about 50 nm to about150 nm and the thickness of the amorphous silicon layer should rangefrom about 15 nm to about 75 nm. The thickness of the amorphous siliconlayer, however, is particularly dependent on the thickness of the firstelectrode layer that will subsequently be deposited thereon. Forexample, if the subsequently deposited first electrode layer comprisescobalt, it takes approximately 3.6 nm of silicon for every 1 nm ofcobalt to form about 3.5 nm of cobalt silicide. If one were wishing touse cobalt silicide as the first electrode, one could use this ratio tochoose a particular thickness of the amorphous silicon layer.

Turning now to FIG. 4, illustrated is a cross-sectional view of thepartially completed semiconductor device 200 illustrated in FIG. 3 afterformation of lightly doped extension implants 410 within the substrate310. The lightly doped extension implants 410 are conventionally formedand generally have a peak dopant concentration ranging from about 1E19atoms/cm³ to about 2E20 atoms/cm³. As is standard in the industry, thelightly doped extension implants 410 have a dopant type opposite to thatof the well region 230 they are located within. Accordingly, the lightlydoped extension implants 410 are doped with a P-type dopant in theillustrative embodiment shown in FIG. 4.

Turning now to FIG. 5, illustrated is a cross-sectional view of thepartially completed semiconductor device 200 illustrated in FIG. 4 afterformation of conventional gate sidewall spacers 510 and after formationof highly doped source/drain implants 520 within the substrate 210. Theformation of the gate sidewall spacers 510, such as Hdd offset spacers,is conventional. Often the gate sidewall spacers 510 comprise a chemicalvapor deposition (CVD) oxide and/or nitride material that has beenanisotropically etched.

Similarly, the highly doped source/drain implants 520 may beconventionally formed. Generally the highly doped source/drain implants520 have a peak dopant concentration ranging from about 1E18 atoms/cm³to about 1E21 atoms/cm³. Also, the highly doped source/drain implants520 should typically have a dopant type opposite to that of the wellregion 230 they are located within. Accordingly, in the illustrativeembodiment shown in FIG. 5, the highly doped source/drain implants 520are doped with a P-type dopant.

Turning now to FIG. 6, illustrated is a cross-sectional view of thepartially completed semiconductor device 200 illustrated in FIG. 5 aftersubjecting it to a standard source/drain anneal, thereby activatingsource/drain regions 610. Uniquely, beyond activating the source/drainregions 610, the standard source/drain anneal also converts theamorphous silicon layer 338 to a recrystallized polysilicon layer 620.It is believed that a source/drain anneal conducted at a temperatureranging from about 1000° C. to about 1100° C. and a time period rangingfrom about 1 second to about 5 seconds would be sufficient to accomplishboth tasks. It should be noted that other temperatures, times, andprocesses could be used to active the source/drain regions 610 as wellas convert the amorphous silicon layer 338 to a recrystallizedpolysilicon layer 620.

Turning now to FIG. 7, illustrated is a cross-sectional view of thepartially completed semiconductor device 200 illustrated in FIG. 6 afterdepositing a first electrode layer 710 on the recrystallized polysiliconlayer 620. The first electrode layer 710 in the embodiment shown in FIG.7 happens to be a thin cobalt layer, however, other materials that reactwith silicon to form a silicide could easily be used.

The first electrode layer 710 of FIG. 7 was conventionally deposited toa thickness ranging from about 4 nm to about 20 nm. Following thedeposition of the first electrode layer 710, an optional capping layer720 could be deposited thereover. The capping layer 720, which may havea thickness ranging from about 5 nm to about 30 nm, may comprise anumber of different materials. For instance, without limiting thepresent invention to such, the capping layer 720 could comprise titaniumor titanium nitride.

It should be mentioned that prior to forming the first electrode layer710 the upper surface of the recrystallized polysilicon layer 620 may becleaned. While it is not entirely imperative, it is believed that asurface cleaning using a diluted HF solution and/or an in-situ plasma(in the same cluster tool as the deposition chamber) would benefit theinterface between the recrystallized polysilicon layer 620 and the firstelectrode layer 710.

Turning now to FIG. 8, illustrated is a cross-sectional view of thepartially completed semiconductor device 200 illustrated in FIG. 7 aftersubjecting it to a first rapid thermal anneal (RTA) process and a selectetch to remove un-reacted first electrode layer 710 on dielectricsurface (such as sidewall and isolation) as well as an optional cap.This first RTA process attempts to cause the first electrode layer 710to react with the recrystallized polysilicon layer 620 to form asilicide 810. In the instance where the first electrode layer 710comprises cobalt, the first RTA process causes the cobalt to react withthe recrystallized polysilicon layer 620 to form CoSi.

The first RTA process may be conducted using a variety of differenttemperatures and times. Nonetheless, it is believed that the first RTAprocess, in an exemplary embodiment, should be conducted in a rapidthermal processing tool at a temperature ranging from about 400° C. toabout 600° C. for a time period ranging from about 5 second to about 60seconds. The specific temperature and time period are typically based,however, on the ability to form the silicide 810 to a desired thickness.

The thickness of the resulting silicide 810 and recrystallizedpolysilicon layer 620 will most likely be different from the originalfirst electrode layer 710 and original recrystallized polysilicon layer620, respectively. It is believed that the resulting silicide layershould have a thickness ranging from about 8 nm to about 40 nm and theremaining recrystallized polysilicon layer 620 should have a thicknessranging from about 7 nm to about 35 nm. This is a result of the silicide810 consuming at least a portion of the original recrystallizedpolysilicon layer 620.

After forming the silicide 810 to a desired thickness, a selective etchis used to remove any un-reacted first electrode layer 710, as well asremove the capping layer 720. The selective etch, among others, couldcomprise a H₂SO₄—H₂O₂—H₂O solution. What remains after the selectiveetch is the silicide 810, which in this embodiment comprises CoSi.

Turning now to FIG. 9, illustrated is a cross-sectional view of thepartially completed semiconductor device 200 illustrated in FIG. 8 aftersubjecting it to a second rapid thermal anneal (RTA) process. Thissecond RTA process attempts to cause the silicide layer 810 to furtherreact with the recrystallized polysilicon layer 620 to form a silicidelayer 910. In the instance where the silicide layer 810 comprises CoSi,the second RTA process causes the CoSi to further react with therecrystallized polysilicon layer 620 to form CoSi₂. In this instance,the CoSi₂ has a substantially lower resistivity than the CoSi formed bythe first RTA process.

The second RTA process may also be conducted using a variety ofdifferent temperatures and times. Nonetheless, it is believed that thesecond RTA process, in an exemplary embodiment, should be conducted in arapid thermal processing tool at a temperature ranging from about 700°C. to about 900° C. for a time period ranging from about 5 second toabout 60 seconds.

After completing the silicide layer 910, the manufacture of thecapacitor would continue in a conventional manner. Specifically, aninsulator and a second electrode would be formed over the silicide layer910. What results after completion of the capacitor is a device similarto the semiconductor device 100 illustrated in FIG. 1.

Turning now to FIG. 10, illustrated is a graph 1000 illustrating some ofthe advantages that may be obtained by forming the lower electrode ofthe capacitor directly on the recrystallized polysilicon layer. Graph1000 of FIG. 10 illustrates the sheet resistance (Rs) and surfacenonuniformity (NU %) for three different situations. Moving from left toright, situation 1 represents an instance where the lower electrode isformed directly on a standard polysilicon layer. Conversely, situation 2represents an instance where the gate electrode only comprises arecrystallized polysilicon layer, and the first electrode layer isformed directly on the recrystallized polysilicon layer. Situation 3, onthe other hand, represents an instance where the gate electrodecomprises a gate electrode stack comprising both the recrystallizedpolysilicon layer and the polysilicon layer, and the first electrode islocated on the recrystallized polysilicon layer and over the polysiliconlayer.

With reference to graph 1000, notice how the sheet resistance andsurface nonuniformity are highest for situation 1. For instance,situation 1 shows a sheet resistance of about 32 ohms/sq and a surfacenonuniformity of about 8%. In contrast, situation 3 shows a sheetresistance of only about 24 ohms/sq and a surface nonuniformity of onlyabout 5%. Similarly, situation 2 shows a sheet resistance of only about21 ohms/sq and a surface nonuniformity of about 4%. Clearly then, theuse of the recrystallized polysilicon layer has its advantages. It isbelieved that the smoother surface of the recrystallized polysiliconlayer, as compared to the standard polysilicon layer, helps providethese superior results.

Turning briefly to FIG. 11, illustrated is a table 1100 showing thesurface roughness measured using an atomic force microscope (AFM) ofsamples similar to situations 1-3 described above. Notice how thesurface roughness, in RMS (nm), measures about 3.0000 for situation 1,1.621 for situation 2, and 2.064 for situation 3. Again, the advantagesare apparent.

One might ask, at least in view of the information provided in FIGS. 10and 11, why not use only a recrystallized polysilicon gate electrode,similar to situation 2, as it provides the best sheet resistance andsurface nonuniformity of the three situations. While the presentinvention does not wish to exclude this option, it has been observedthat a gate electrode only formed of recrystallized polysilicon has alower inversion capacitance. It is believed that this lower inversioncapacitance is caused by the increased poly depletion, which may becaused by the much slower diffusion of the gate electrode dopant in therecrystallized polysilicon than in the standard polysilicon thatconsists of columnar grains. This, in effect, hampers the ability of thegate electrode dopant, such as boron, to diffuse to the gateelectrode/gate oxide interface. This idea is illustrated in FIG. 12. Thebi-layer stack, that is polysilicon at the bottom of the gate electrodewith a layer of recrystallized polysilicon thereover (e.g., situation 3)would address this problem.

Referring finally to FIG. 13, illustrated is an exemplarycross-sectional view of a conventional integrated circuit (IC) 1300incorporating devices 1310 constructed according to the principles ofthe present invention. The IC 1300 may include devices, such astransistors used to form CMOS devices, BiCMOS devices, Bipolar devices,as well as capacitors or other types of devices. The IC 1300 may furtherinclude passive devices, such as inductors or resistors, or it may alsoinclude optical devices or optoelectronic devices. Those skilled in theart are familiar with these various types of devices and theirmanufacture. In the particular embodiment illustrated in FIG. 13, the IC1300 includes the devices 1310 having dielectric layers 1320 locatedthereover. Additionally, interconnect structures 1330 are located withinthe dielectric layers 1320 to interconnect various devices, thus,forming the operational integrated circuit 1300.

Although the present invention has been described in detail, thoseskilled in the art should understand that they can make various changes,substitutions and alterations herein without departing from the spiritand scope of the invention in its broadest form.

1. (canceled)
 2. A semiconductor device, comprising: a recrystallizedpolysilicon layer located over a gate electrode layer; and a capacitorlocated on said recrystallized polysilicon layer, said capacitor,including; a first electrode; an insulator located over said firstelectrode; and a second electrode located over said insulator. whereinsaid first electrode comprises a silicide.
 3. The semiconductor deviceas recited in claim 2 wherein said first electrode comprises cobaltsilicide.
 4. The semiconductor device as recited in claim 2 wherein saidfirst electrode has a surface roughness ranging from about 1 nm to about2 nm.
 5. A semiconductor device, comprising: a recrystallizedpolysilicon layer located over a gate electrode layer; and a capacitorlocated on said recrystallized polysilicon layer, said capacitor,including; a first electrode; an insulator located over said firstelectrode; and a second electrode located over said insulator; whereinat least a portion of said recrystallized polysilicon layer forms aportion of said first electrode.
 6. The semiconductor device as recitedin claim 5 wherein said recrystallized polysilicon layer has a finalthickness ranging from about 7 nm to about 35 nm.
 7. A semiconductordevice, comprising: a recrystallized polysilicon layer located over agate electrode layer; and a capacitor located on said recrystallizedpolysilicon layer, said capacitor, including; a first electrode; aninsulator located over said first electrode; and a second electrodelocated over said insulator; wherein said gate electrode layer is apolysilicon layer and said recrystallized polysilicon layer is locatedon said polysilicon layer.
 8. The semiconductor device as recited inclaim 7 wherein said polysilicon layer and said recrystallizedpolysilicon layer form at least a portion of a gate electrode stack. 9.A method for manufacturing a semiconductor device, comprising: formingan amorphous silicon layer over a substrate; changing said amorphoussilicon layer to a recrystallized polysilicon layer; and creating acapacitor on said recrystallized polysilicon layer, said capacitorincluding; a first electrode; an insulator located over said firstelectrode; a second electrode located over said insulator.
 10. Themethod as recited in claim 9 wherein forming an amorphous silicon layerincludes depositing an amorphous silicon layer having a thicknessranging from about 15 nm to about 75 nm.
 11. The method as recited inclaim 9 wherein changing said amorphous silicon layer to arecrystallized polysilicon layer includes subjecting said amorphoussilicon layer to an annealing process, said annealing process causingsaid amorphous silicon layer to become said recrystallized polysiliconlayer.
 12. The method as recited in claim 11 wherein subjecting saidamorphous silicon layer to an annealing process includes subjecting saidamorphous silicon layer to a temperature ranging from about 1000□ C toabout 1100□ C.
 13. The method as recited in claim 9 wherein forming anamorphous silicon layer over a substrate includes forming an amorphoussilicon layer on a polysilicon layer, wherein said amorphous siliconlayer and said polysilicon layer form at least a part of a gateelectrode stack.
 14. The method as recited in claim 13 wherein saidamorphous silicon layer has a thickness ranging from about 15 nm toabout 75 nm and said polysilicon layer has a thickness ranging fromabout 50 nm to about 150 nm.
 15. The method as recited in claim 9wherein creating a capacitor first electrode includes creating acapacitor first electrode comprising a silicide.
 16. The method asrecited in claim 14 wherein said silicide comprises cobalt silicide. 17.The method as recited in claim 9 wherein creating a capacitor firstelectrode includes creating a capacitor first electrode having a surfaceroughness ranging from about 1 nm to about 2 nm.
 18. The method asrecited in claim 9 wherein creating a capacitor first electrode includescreating a capacitor first electrode having a thickness ranging fromabout 15 nm to about 70 nm.
 19. An integrated circuit, comprising:transistors located over a substrate, wherein at least one of saidtransistors includes a gate electrode stack comprising a recrystallizedpolysilicon layer located over a gate electrode layer; a capacitorlocated on said recrystallized polysilicon layer, said capacitorincluding; a first electrode; an insulator located over said firstelectrode; and a second electrode located over said insulator; and aninterlevel dielectric layer located over said substrate, said interleveldielectric layer having interconnects located therein for contacting atleast one of said gate electrode stack or said capacitor.
 20. Theintegrated circuit as recited in claim 18 wherein at least a portion ofsaid recrystallized polysilicon layer forms a portion of said firstelectrode.
 21. The integrated circuit as recited in claim 18 whereinsaid transistors are selected from the group consisting of: a CMOStransistor; a bipolar transistor; and a biCMOS transistor.